1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device.
2. Description of the Prior Art
Generally, a core semiconductor device is supplied with power less than or equal to 3.3V in order to reduce power consumption and ensure reliability. However, such devices are generally connected to peripheral devices, which may receive a different power supply, in one system.
Further, since the peripheral devices are supplied with a high voltage of 5V or above, many integrated circuits (IC's) include a high-voltage transistor to support a high input voltage supplied from an exterior.
Such a high-voltage transistor has the same structure as that of a normal (e.g., low-voltage) MOS transistor, and can be formed substantially simultaneously with the low-voltage transistor in-situ.
Meanwhile, certain bi-directional high-voltage devices having an operational level of about 13.5V can be integrated in a chip together with a low-voltage device. Such a high-voltage device can be used for an output terminal of a data driver IC for a liquid crystal display (LCD) or an organic luminescence electro display (OLED). Thus, the bi-directional high-voltage device must be flexibly available for a low-voltage operation and have a superior analog output characteristic.
In particular, an exemplary number of output terminals of one display driver IC can be from 240 to 640, and the uniformity of the output terminals directly exerts an influence upon the uniformity of the display quality, so uniformity of the electrical characteristics of the output terminal is a very important factor.
FIG. 1 is a sectional view showing a conventional semiconductor device.
As shown in FIG. 1, a conventional high-voltage semiconductor device may include a semiconductor substrate 1, a high-voltage P-well 2 provided on the semiconductor substrate 1, a field oxide layer 3 for defining an active area, a gate electrode 4 formed in the active area, source/drain areas 6 formed in the semiconductor substrate 1, and drift areas 5 surrounding the source/drain area 6 in order to stabilize a breakdown voltage.
Hereinafter, a conventional method for manufacturing the semiconductor device of FIG. 1 will be described. First, a high-voltage N-well (not shown), a high-voltage P-well 2, a low-voltage N-well (not shown), and a low-voltage P-well (not shown) are formed in the semiconductor substrate 1.
Then, N-drift areas 5 and corresponding P-drift areas (not shown) are formed on the surfaces of the high-voltage P-well 2 and the high-voltage N-well (not shown), respectively.
In addition, after forming the field oxide layer 3 and performing an ion-implantation process for adjusting threshold voltages of high-voltage PMOS transistors, low-voltage NMOS transistors, and low-voltage PMOS transistors, gate oxide layers of the high-voltage and low-voltage transistors are formed.
Then, a gate conductive layer is deposited and patterned, thereby forming the gate electrode 4.
Finally, LDD areas of low-voltage NMOS and PMOS transistors are formed through an ion-implantation process, and then source/drain areas 6 of the high-voltage and low-voltage transistors are formed.
However, the above conventional method has following disadvantages.
Since the drift area has been already realized before the gate electrode is formed, the high-voltage device is not self-aligned. Accordingly, when the channel area is narrowed, voltage differences for various transistor parameters may vary for each semiconductor device.